cvs commit: src/sys/amd64/amd64 cpu_switch.S machdep.c
bde at zeta.org.au
Thu Oct 20 04:11:43 PDT 2005
On Thu, 20 Oct 2005, David Xu wrote:
> Bruce Evans wrote:
>> I wonder if this reduces the context switch latency from about 1.320
>> usec to 0.900 usec on my A64-3000. The latency is only .520 usec in
>> i386 mode. I use a TSC timecounter of course.
> we can avoid reloading userland GS.base MSR and FS.base MSR for system
> threads, I am not sure if it can reduce interrupt thread latency.
I think it would recover some of the the other 0.400 usec of the extra
overhead for the amd64 case.
We already avoid null reloads of %cr3 and avoiding null reloads of
FS/GS.base would be similar. Both are null only for intra-kernel
switches, so the savings are smaller than for the stores of FS/GS.base
since the reloads can't always be avoided.
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