cvs commit: src/sys/i386/isa clock.c

[Mike Silbersack]

On Sat, 1 May 2004, Bruce Evans wrote:

> On Sat, 1 May 2004, Mike Silbersack wrote:
>
> >                         delta += timer0_max_count;
>
> I think you missed that the hardware timer is count-down.  We don't assume
> anything about entire counter cycles; we just miss them and wait another
> timer0_max_count cycles.  The adjustment by timer0_max count is just to
> to convert the counter from count-down to count-up.  it works right for
> that:

Gah, yeah, I wasn't awake enough when I was reading the code last night.
I had been reading that line as "delta = timer0_max_count", rather than
+=.  The code makes sense to me now.

> HZ=1000 instead of the default of HZ=10 increases the chance of the
> timer wrapping while DELAY() is interrupted.  This shouldn't be a
> problem for TSC calibration.

Apparently it is a problem, somehow. :)

I am using HZ=1000 on the trouble system, FWIW.

> My version of TSC calibration uses a much more precise algorithm.  It
> still uses the i8254 since this is the best clock to compare with
> for technical reasons.  I will send this in private mail.  You could
> also try RELENG_4 to get calibration of the TSC relative to the RTC.
> This is more precise than the current calibration, but may be less
> accurate since the nominal RTC frequency may be less accurate than
> the nominal i8254 frequency.
>
> Bruce

I tried the first patch and it didn't help, I may give the second patch a
go after I finish up some (non-freebsd) work.

Mike "Silby" Silbersack