cvs commit: src/sys/ia64/include float.h

[Marcel Moolenaar]

On Wed, Apr 02, 2003 at 04:12:50PM -0800, David Schultz wrote:
> 
> > Note also that the 82-bit FP registers have a 17-bit exponent to aid
> > in near-overflow and near-underflow computations in IEEE754 double-
> > extended format. Of course an exception is still raised if the result
> > does not fit the target if the target is in double-extended format.
> 
> Right.  I think the LDBL_{MIN,MAX}* constants need to refer to the
> memory format, not the FPU-internal format.

Agreed.

> If we *really* want
> to be pedantic, we can clear the WRE bit in the FPU control
> register and sacrifice the extra range in the interests of being
> predictable.

This is already the default, except for SF1. SF1 is documented
to be reserved for math library implementations and has WRE
enabled by default.

> That's similar to what we do with i386 now, where we
> sacrifice precision so gcc bugs don't cause strange things to
> happen in the lower echelons.  It's rather annoying.  We don't
> change the default precision control setting on IA64, do we?

Correct, we don't.

-- 
 Marcel Moolenaar	  USPA: A-39004		 marcel at xcllnt.net