cvs commit: ports/cad/p5-Verilog-Perl Makefile distinfo

[Philip M. Gollucci]

pgollucci    2010-01-18 00:57:34 UTC

  FreeBSD ports repository

  Modified files:
    cad/p5-Verilog-Perl  Makefile distinfo 
  Log:
  - Update to 3.223
  
  PR:             ports/142626
  Submitted by:   myself (pgollucci@)
  Approved by:    otacilio.neto at ee.ufcg.edu.br (maintainer)
  
  Revision  Changes    Path
  1.9       +1 -1      ports/cad/p5-Verilog-Perl/Makefile
  1.6       +3 -3      ports/cad/p5-Verilog-Perl/distinfo