cvs commit: ports/cad/verilog-mode.el Makefile distinfo

Pawel Pekala pawel at FreeBSD.org
Mon Apr 16 20:20:33 UTC 2012


pawel       2012-04-16 20:20:32 UTC

  FreeBSD ports repository

  Modified files:
    cad/verilog-mode.el  Makefile distinfo 
  Log:
  Update to 790
  
  PR:             ports/166209
  Submitted by:   Lowell Gilbert <lowell at be-well.ilk.org>
  
  Revision  Changes    Path
  1.4       +1 -2      ports/cad/verilog-mode.el/Makefile
  1.3       +2 -2      ports/cad/verilog-mode.el/distinfo


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