test at Target mode
isshi at cs.fujitsu.co.jp
Thu Aug 2 03:39:39 PDT 2001
I doubted the hardware, but I cannot prove it.
It's reassuring that Adaptec co. is backing up.
When I questioned Adaptec co. on AIC7xxx assembler before,
they said that the information cannot be opened.
Now It's pleased to find opened ML and the assembler.
Without CAM, target I/O system can be implemented under 6.1.13.
I have some changes:
1)When any abort message is received, sequencer should go to BusFree.
2)When any abort message is received, sequencer should set SAVED_LUN.
3)When ABORT message(=1 bytes message) is received,
driver cannot get it because ATNI is off.
"Justin T. Gibbs" wrote:
> >When the 2nd BusReset continues to occur, ENSELI bit in SCSISEQ is reset by
> >anyone.Do you know who reset it?
> After checking with a hardware engineer, it appears that the chip (
> at least the 7899, but perhaps some of the older ones too)
> automatically resets this bit on either an outgoing or incoming
> bus reset. In 6.2.0, I've chnaged the target mode reset behavior
> to re-enable the interrupt immediately after we see a reset. This
> leaves us open to the "interrupt storm" problems I listed before,
> but at least ensures that we will always respond to selection. Targets
> are supposed to respond to selection "as soon as possible" after a
> reset, so reducing the interrupt rate by setting a timer to re-enable
> select-ins every few milliseconds probably wouldn't cut it. I'll
> have to go review the SPI-4 and SAM-2 specs again.
To avoid "interrupt storm" , I inserted a delay timer temporarily.
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